This disclosure relates to improving power consumption in a region of programmable logic of an integrated circuit while providing sufficient clock frequency to the region to support a design programmed into the region of the programmable logic.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it may be understood that these statements are to be read in this light, and not as admissions of prior art.
In certain integrated circuits that do not contain programmable logic fabric, minimum operating voltages or clock frequencies may be identified by testing the integrated circuits during the manufacturing process. An integrated circuit that contains programmable logic fabric, however, provides a highly flexible platform that can be configured after manufacturing with a custom circuit design. The flexibility and variability in the possible designs that may be programmed into this type of integrated circuit, however, also makes identifying the lowest potential operating voltages or clock frequencies during much more difficult—potentially even impossible—since there may be no way of knowing during manufacturing what circuit design will be ultimately programmed into the programmable logic fabric of the integrated circuit.